Micro-fluidic ejection devices typically include a silicon substrate material that includes “flow features,” for example, fluid openings, fluid passages, holes, trenches, or depressions, formed therein. These flow features may be formed by a wide variety of micromachining techniques including sand blasting, wet chemical etching and reactive ion etching. As these devices become smaller, such as for ink jet printhead applications, micromachining of the substrates becomes a more critical operation.
One micromachining technique of particular interest is a silicon dry etch technique known as Deep Reactive Ion Etch (DRIE). DRIE has the potential to create deep and narrow holes through a silicon wafer. DRIE can routinely produce aspect ratios as high as 25:1, which can be critical in creating holes that are closely spaced, such as is needed for high-resolution ink jet printhead devices. DRIE goes by many names in the literature; however, herein we are referring specifically to the Bosch process that features sequential ionic plasma etch and passivation layer deposition. This technique offers high drilling rates with vertical sidewalls and high aspect ratio (height/width).
Some of the drawbacks of the DRIE process include an aspect ratio dependent etching rate. This means that the rate of drilling is slower for small diameter holes than it is for larger diameter holes. Variability in etching rate is also found when comparing holes made in the center of the silicon wafer to the edges of the wafer (commonly referred to as the bulls-eye effect). Microloading is another known issue in which isolated holes will drill somewhat faster than holes that are situated nearby to other holes. When holes are being drilled all the way through the silicon wafer from one surface to the other, these rate differences may not matter too much. However, certain MEMS applications require that a silicon substrate have holes that are drilled down to an insulating layer, which serves as an etch stop or as a device functional layer. When hole drilling stops at an insulating layer on the surface of the wafer, such as is found in Silicon on Insulator (SOI) substrates, variability in the etch rate often leads to additional defects.
In particular, when SOI wafers are etched using DRIE, notching occurs. Referring to FIG. 9a, notching, which is present in region 930, is the phenomenon of localized undercutting of the silicon at the silicon/insulator boundary. It is widely believed that this phenomenon is caused by local charging of the insulating layer 960 by plasma ions in region 980 which causes lateral deflection of the ionic species resulting in lateral etching of the sidewalls in region 930. Notching can also be understood, more elementarily, as caused by over etching, especially where some of the holes in a wafer reach the insulating layer before the etching process is complete due to etching rate variability described previously.
A number of countermeasures to reduce or even prevent notching have been proposed. One widely used technique is to observe when the hole approaches the insulating layer and then alter the DRIE parameters to reduce the etching rate. This approach works well when there are uniform hole etching rates, but even then, requires difficult or complex monitoring techniques to know when to reduce the etch rate without unduly sacrificing productivity.
Several approaches using changes in pulse duty cycle or frequency have been found to reduce notching, but changes in optimized etching process parameters are likely to have a negative impact on etching characteristics such as etch rate or anisotropy. Another approach is to add a metallization layer to the insulator to avoid charge build up, but that adds manufacturing complexity, especially if that metal layer must be removed after the DRIE is complete.
As such, there is an ongoing need to develop a solution in which the insulating layer itself reduces or even prevents notching preferably without adding additional complexity or cost to the process or the finished product.